Data integrity is an essential feature for any data storage device. Use of strong error-correction codes (ECCs) is recommended for NAND flash memory devices as the storage density increases with the use of multi-level cell/triple level cell (MLC/TLC) NAND flash. Low-Density Parity-Check (LDPC) codes are often used as the ECC scheme in storage devices. Moreover, Quasi-Cyclic LDPC (QC-LDPC) codes that have circulant permutation matrices as sub-matrices in their parity-check matrix are often preferred because they allow simple implementations of the encoding and decoding algorithms.
During code design, the parity-check matrix for a LDPC code is typically constructed with random computer search or algebraic constructions to give best decoding performance. These construction methods may not lead to a parity-check matrix which has the structure preferred for an efficient encoder. Constraining the parity-check matrix to have a preferred structure during code construction may limit the decoding performance. Accordingly, existing systems may use a parity-check matrix optimized for an LDPC decoder, but not for an LDPC encoder. Although properly encoding bits, the sub-optimal use of the LDPC encoder may result in relatively larger memory usage and power consumption.